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ASIC Physical Design Intern

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  • Internship
    Full-time
    Summer Internship
  • Engineering
    IT & Cybersecurity
  • Boxborough

Requirements

  • Knowledge of basic circuits and logic design.
  • Proficiency in a scripting language (e.g., Perl, Python, or Tcl).
  • Understanding of timing analysis and placement and route tools.
  • Familiarity with Verilog and low power design techniques is a plus.
  • Completed at least 2 semesters of university coursework in Electrical Engineering, Computer Engineering, Computer Science, Applied Physics, or a similar technical field.
  • Detail-oriented and analytical with a strong problem-solving mindset.
  • Eager to learn and contribute to innovative design flows.
  • Capable of documenting and coding to improve design environments.
  • Enthusiastic about collaborating with a dynamic team.
  • Able to commute to our Boxborough, MA office.

Responsibilities

  • Learning the design flows that enable physical design activities of high-speed IPs such as DDR/UCIe/HBMs at cutting-edge technology nodes.
  • Analyzing and documenting the static timing environment of high-speed logic and/or custom circuits.
  • Coding to improve the static timing environment of high-speed logic and/or custom circuits.
  • Collaborating with the MSIP ASIC Physical Design Implementation team to integrate more capabilities into an SoC.
  • Gaining hands-on experience with placement and route tools, timing analysis, and low power design techniques.
  • Contributing to the development and verification of gate-level design and electrical reliability of physical design.

FAQs

What is the job title for this position?

The job title for this position is ASIC Physical Design Intern.

What educational background is required for this internship?

Candidates should be pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, Applied Physics, or a similar technical field, and must have completed at least 2 semesters of university coursework.

What skills are necessary for this internship?

Necessary skills include knowledge of basic circuits and logic design, proficiency in a scripting language (such as Perl, Python, or Tcl), and an understanding of timing analysis and placement and route tools. Familiarity with Verilog and low power design techniques is a plus.

What type of projects will the intern work on?

The intern will work on analyzing and documenting the static timing environment of high-speed logic and/or custom circuits, improving design flows for high-speed IPs, and collaborating with the MSIP ASIC Physical Design Implementation team.

Where is the internship located?

The internship is located in Boxborough, MA.

What kind of team will the intern be a part of?

The intern will be part of the MSIP ASIC Physical Design Implementation team, which focuses on integrating capabilities into an SoC and delivering differentiated products to market quickly.

Is previous experience required for this position?

No previous experience is required, but a solid understanding of the relevant concepts and a passion for learning are essential.

What is the expected pay range for this internship?

The base salary range for this role is between $32.00 and $46.00 per hour.

Are there opportunities for learning and career development in this role?

Yes, this role offers hands-on experience and a solid foundation of knowledge and skills in ASIC Physical Design, preparing interns for a successful career in the industry.

Will the intern have the opportunity to collaborate with other teams?

Yes, the intern will collaborate with the MSIP ASIC Physical Design Implementation team and contribute to integrating capabilities into an SoC.

How does Synopsys support its employees' wellness and financial benefits?

Synopsys offers comprehensive wealth, wellness, and financial benefits as part of a competitive rewards package, which may include an annual bonus, equity, and other discretionary bonuses.

What qualities does the ideal candidate possess?

The ideal candidate is detail-oriented, analytical, eager to learn, and enthusiastic about collaborating with a dynamic team.

Powering the New Era of Smart Everything—from Silicon to Software

Technology
Industry
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Employees

Mission & Purpose

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every day.

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