Logo of Huzzle


FPGA Development Intern/Co-op (Fall 2024)

Logo of Ciena


15d ago

🚀 Off-cycle Internship


AI generated summary

  • You must have a sense of urgency, integrity, commitment to innovation, adaptability, ability to work independently and in a team. Must have a Bachelor's in EE or CE, knowledge of circuit design, and experience with Verilog, Python, and FPGA tools.
  • You will design and verify FPGAs using SystemVerilog/UVM, write technical documentation, and manage the FPGA design life cycle daily.

Off-cycle Internship

Software EngineeringOttawa


  • The FPGA development team is seeking eligible co-op candidates to participate in the design, test, and support of optical networking products. You will be introduced to FPGA design and verification methodologies where we place a significant emphasis on early in career development through our FPGA curriculum and mentorship programs.


  • A sense of urgency – what’s important to the customer is equally important to you. You make getting things done a priority.
  • Integrity – you hold yourself to the highest level of personal and professional standards of conduct.
  • A commitment to innovation – you continually seek to learn, understand new technologies and ever-changing market conditions, and endeavour to apply that knowledge to Ciena’s advantage.
  • You embrace change – thriving in a diverse environment of ever-changing priorities and sometimes stressful situations.
  • The flexibility to work independently with minimal supervision as well as part of a broader team.
  • The Must Haves:
  • Working towards completion of a Bachelor’s degree in Electrical Engineering, Computer Engineering or equivalent.
  • Foundational knowledge of circuit design and digital logic.
  • Excellent verbal and written communication skills.
  • Assets:
  • Familiarity with the following:
  • Hardware description languages such as Verilog or SystemVerilog.
  • Scripting and command languages such as Python, TCL, or Bash.
  • FPGA development tools such as Questa, VCS, Quartus, or Vivado.

Education requirements

Currently Studying

Area of Responsibilities

Software Engineering


  • FPGA design using SystemVerilog for AMD, Intel, and Lattice FPGAs.
  • FPGA verification using Universal Verification Methodology (UVM).
  • Technical documentation writing and datasheet analysis.
  • The life cycle of an FPGA design from concept to release.


Work type

Full time

Work mode