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Hardware Engineering Intern (Summer 2024)

🚀 Summer Internship

San Jose

AI generated summary

  • You need expertise in Verilog, FPGA design, AMD/Xilinx tools, Linux, scripting, communication, and debugging for the Hardware Engineering Intern role at Cadence Design Systems next summer.
  • You will work on ASIC verification through simulation, gate level testing, code coverage, and debugging. Develop embedded processor code and debug system software on custom ASICs.

Summer Internship

EngineeringSan Jose


  • Cadence Design Systems is looking for a highly motivated engineer to work as a member of the R&D staff on Cadence verification tool  platforms focusing on elevating its tools, Xcelium, Verisium, Palladium etc… to new orders of efficiency and scalability. We are looking for skilled and motivated candidates with background in Electrical Engineering.


  • Current BS or MS student majoring in Electrical Engineering or equivalent with courses in design/verification using Verilog
  • Knowledge and hands on projects in FPGA design and verification
  • Experience AMD/Xilinx Vivado tools (Place and Route, Hardware Manager) desirable
  • Experience using Linux servers, Script development using Shell/Perl/TCL
  • Good communication skills
  • Good debugging skills

Education requirements

Currently Studying

Area of Responsibilities



  • Work on Simulation/Emulation based verification of complex ASICs
  • Use code coverage / formal verification tools as part of the ASIC verification process
  • Run and debug gate level simulations
  • Understand rtl implementation of digital circuits described with Verilog/VHDL
  • Develop embedded processor code for in system post silicon testing
  • Debug SW/FW on system that uses custom ASICs


Work type

Full time

Work mode



San Jose