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Intern, Logic Pathfinding Lab Advanced DTCO Engineer

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Samsung Semiconductor

1mo ago

  • Internship
    Full-time
    Summer Internship
  • Engineering
    IT & Cybersecurity
  • San Jose
  • Quick Apply

AI generated summary

  • You must be a grad student in VLSI tech, have DTCO experience, proficiency in programming, and exhibit curiosity, collaboration, and innovation in your approaches.
  • You will conduct block-level design for 2D/3D ICs, analyze power drop, improve DTCO metrics, evaluate methodologies, transfer flows from Georgia Tech, and assess memory latency impacts.

Requirements

  • Graduate student enrolled in a Master or PhD program with academic focus in VLSI technology and design
  • Must have at least 1 academic quarter/semester remaining
  • Working experience on DTCO including standard cell design, library generation and characterization, and Place and Route
  • Working experience on VLSI workload modeling and the implications on the logic and packaging technologies
  • Proficient in programming
  • You're inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Responsibilities

  • Block-level physical design flow for 2D and 3D ICs
  • Apply vector-based power and dynamic IR drop analysis for 2D IC reference circuits
  • Propose new or improve existing metrics for logic DTCO, considering workload and system level considerations
  • Evaluate pros and cons of different DTCO methodologies for 2D IC
  • Transfer advanced DTCO flow and examples from Georgia Tech, for 2D / 3D IC
  • Bring in relevant testcases from Georgia Tech – LPL collaboration for analysis and identify bottlenecks due to technology
  • Identify impact of memory (SRAM) latency and bandwidth on system level performance
  • Collaborate closely with Samsung DTCO engineers
  • Complete other responsibilities as assigned.

FAQs

Do we support remote work?

This position is onsite at our San Jose headquarters 5 days a week.

What qualifications do I need to apply for this internship?

You must be a graduate student enrolled in a Master or PhD program with an academic focus in VLSI technology and design, and have at least 1 academic quarter/semester remaining.

What skills will I learn during this internship?

You will learn about advanced design technology co-optimization for 2D and 3D IC, DTCO techniques, PPA analysis and interpretation, and PDK customization for 3D IC applications.

What type of projects will I be working on?

You will work on block-level physical design flows for 2D and 3D ICs, conduct power and IR drop analysis, and propose improvements for logic DTCO metrics.

Will I have the opportunity to collaborate with other engineers?

Yes, you will collaborate closely with Samsung DTCO engineers as part of your responsibilities.

Is there a limit on the number of job applications I can submit?

Yes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Does the internship require programming experience?

Yes, proficiency in programming is required for this position.

Are there any specific methodologies I need to evaluate for this role?

You will need to evaluate the pros and cons of different DTCO methodologies for 2D IC.

What is the company's stance on diversity and inclusion?

Our company is dedicated to fostering an inclusive culture and a diverse workforce, empowering people to be their true selves.

What are the COVID-19 policies for employees?

We encourage vaccination for all employees and may require it depending on job functions. Employees must complete a daily health questionnaire and weekly COVID tests while visiting offices or attending team events.

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Samsung Semiconductor

Manufacturing & Electronics
Industry
10,001+
Employees

Mission & Purpose

Established in 1974 as a subsidiary of Samsung Electronics, we’re proud to be recognized as one of the leading chip manufacturers in the world. Using our knowledge in semiconductor technology, our ambition is to spark the imagination of device manufacturers with top-of-the-line building blocks and, through that, enrich the lives of people around the world with transformative solutions.