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Physical Design Methodology - Intern

🚀 Off-cycle Internship

Mountain View

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Off-cycle Internship

IT & CybersecurityMountain View


  • We are looking for an intern in our ASIC PD VLSI Team. This is an excellent opportunity to learn and gain experience in Physical Design and Methodology working on Synthesis, place and route, physical partitions, and hierarchical blocks. This is an exciting opportunity to be part of a fast-paced Startup culture doing world-class ASICs on AI, ML RISC-V based Processor Chips at advanced process technology nodes.  


  • Pursuing Bachelors or Masters in Computer/Electrical/Electronic Engineering or Computer Science.
  • Coursework and strong knowledge of Digital VLSI IC Design, Computer Architecture and CMOS, FINFET devices, etc.
  • Academic projects in Chip design with usage of industry standard EDA tools is a plus.
  • Strong programming skills and usage of scripting languages TCL, Perl, or Python.
  • Familiarity with Linux/Unix design environments.
  • Strong engineering mindset, interpersonal and collaboration skills.

Education requirements

Currently Studying

Area of Responsibilities

IT & Cybersecurity


  • Opportunity to learn and gain knowledge on various industry standard Electronic Design Automation (EDA) tools used in physical design from RTL to GDSII.
  • You will get hands on experience in various ASIC physical implementation stages starting from Floorplan, Synthesis, Place and Route to Extraction, Physical verification, Formal verification, Static Timing Analysis and EMIR Analysis.
  • Opportunity to excel and improve skills in scripting languages commonly used in ASIC design, such as Linux Shell, TCL, Perl, and Python.
  • You will be involved in enhancing the CAD tool methodologies for automation to improve productivity, solve design challenges and to enhance designs for better PPA and QOR.
  • Opportunity to engage and participate in ongoing research and innovation topics improving performance and power efficiency.
  • An ideal position for a career path towards ASIC Engineering with a keen interest in Digital IC design and Backend Physical design.


Work type

Full time

Work mode



Mountain View