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Power Management Design Engineering Intern

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Qorvo, Inc.

11d ago

  • Internship
    Full-time
    Summer Internship
  • Software Engineering
    Engineering
  • Greensboro

AI generated summary

  • You should be pursuing an MS or PhD in Electrical Engineering with a 3.5+ GPA, have analog/RF design experience, Cadence Virtuoso skills, and lab equipment familiarity. Good communication is key.
  • You will design and simulate analog power management blocks, contribute to design teams, evaluate lab data, and present results while meeting performance requirements within size, cost, and schedule constraints.

Requirements

  • Currently pursuing an MS or PhD in Electrical Engineering
  • Minimum GPA of 3.5
  • Analog/RF circuit design coursework and/or experience
  • Experience with Cadence Virtuoso Design System Environment required
  • Highly motivated with good communication skills
  • Excellent written and verbal communication skills
  • Team player and enjoys working in a fast paced environment
  • Familiarity with lab evaluation equipment such as power supplies, multi-meters, and oscilloscopes preferred

Responsibilities

  • Responsibilities may include:
  • Specification, design, and transistor level simulation of analog and power management blocks and sub-systems such as bandgaps, LDOs, and DC-DC converters
  • Working as a member of a design team to contribute design schematics, simulations, and lab evaluation data
  • Meeting circuit performance requirements considering size, cost, and schedule
  • Presenting results in design and evaluation reviews

FAQs

What level of education is required for the Power Management Design Engineering Intern position?

Candidates must be currently pursuing an MS or PhD in Electrical Engineering.

What is the minimum GPA requirement for applicants?

The minimum GPA requirement is 3.5.

Is experience with CAD software necessary for this internship?

Yes, experience with the Cadence Virtuoso Design System Environment is required.

What specific responsibilities will the intern have?

Intern responsibilities include specification, design, and transistor level simulation of analog and power management blocks, contributing to design schematics, simulations, lab evaluation data, and presenting results in design reviews.

Are there opportunities for networking during the internship?

Yes, the internship program offers networking and social events.

Will the intern have exposure to upper management?

Yes, interns will have exposure to upper management as part of the internship experience.

What type of projects will the intern be working on?

The intern will work on projects related to high-performance analog, advanced cellular, and connectivity and sensors, with specific responsibilities determined by business needs.

Is familiarity with lab evaluation equipment preferred?

Yes, familiarity with lab evaluation equipment such as power supplies, multi-meters, and oscilloscopes is preferred.

How will interns present their work?

Interns will present their results in design and evaluation reviews to business leaders.

What is the location of this internship?

The internship is located in Greensboro, NC, at Qorvo's headquarters.

Qorvo, Inc.

Semiconductor solutions that connect, protect and power the world around us

Manufacturing & Electronics
Industry
5001-10,000
Employees
2015
Founded Year

Mission & Purpose

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense.