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Senior FPGA Engineer

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  • Job
    Full-time
    Senior Level
  • Engineering
  • $170K - $235K
  • San Francisco

Requirements

  • Bachelor of Science degree in electrical engineering, computer science, computer engineering, or equivalent
  • 5+ years of experience
  • A passion for hardware development, including working in a fast-paced environment and hands-on design and development
  • Experience in designing, implementing, and testing high throughput systems implemented on FPGAs
  • Familiarity with system level estimates and implications of power, thermal, and real estate
  • Strong proficiency with Verilog/SystemVerilog for both synthesis and verification
  • Writing test benches and FPGA verification at module level and at top/system level
  • Experience with C/C++ bit accurate modeling of RTL modules.
  • Bonus:
  • MS or PhD in computer engineering or equivalent
  • Considerable expertise in at least 1 domain beyond just the logic design. This could be DSP/radio design, software, encryption, FEC encoding/decoding.
  • Experience with Xilinx Ultrascale/Ultrascale+/Versal FPGA’s
  • Experience with Vivado IDE, TCL
  • Experience with high speed data converters (ADCs, DACs, JESD204)
  • Experience with UVM and DPI simulation methodologies
  • Experience with circuit level debugging
  • Experience with digital communication theory and implementation, DVB-S2X modulation/demodulation, FEC encoding/decoding as LDPC, Turbo, Reed-Solomon, Channelization, FIR/IIR filtering, I/Q signaling.
  • Experience with space-based systems, Radiation tolerant design, such as TMR and ECC
  • Experience with a scripting language like Python or Perl or Tcl

Responsibilities

  • Design RTL for high data rate, software defined radios
  • Work with multiple FPGAs and toolchains
  • Interface FPGAs with high speed data converters, memories, MCUs
  • Design, implement and test radiation mitigation schemes on FPGA
  • Collaborate closely with DSP/radio algorithm designers
  • Collaborate closely with embedded firmware and software engineers
  • Assist in recruiting, interviewing, and hiring additional teammates to our rapidly-growing team.

FAQs

What are the main responsibilities of a Senior FPGA Engineer?

The main responsibilities of a Senior FPGA Engineer include architecture, design, verification, and testing of RTL designs for FPGAs used in spacecraft and ground stations. They collaborate closely with software, DSP, and hardware teams to meet design requirements.

What qualifications are required to become a Senior FPGA Engineer?

Typically, a Senior FPGA Engineer would need a bachelor's or master's degree in Electrical Engineering or a related field. They should also have extensive experience in FPGA design, verification, and testing, as well as strong collaboration and communication skills.

What experience is necessary for a Senior FPGA Engineer role?

A Senior FPGA Engineer should have several years of experience working in FPGA design and development, particularly in the aerospace industry. Experience with RTL design, verification, and testing tools is essential. Additionally, experience collaborating with cross-functional teams is a plus.

How important is collaboration in this role?

Collaboration is crucial for a Senior FPGA Engineer as they work closely with software, DSP, and hardware teams to ensure that the FPGA designs meet the overall system requirements. Clear communication and teamwork are essential for successful project outcomes.

What challenges might a Senior FPGA Engineer encounter in their role?

Senior FPGA Engineers may face challenges related to complex FPGA designs, tight project timelines, and integration issues with other system components. Additionally, staying current with evolving FPGA technologies and standards can be a challenge in this role.

Small, low-cost communications satellites, in higher orbits.

201-500
Employees
2015
Founded Year

Mission & Purpose

Astranis is building small, low-cost telecommunications satellites. Our mission is to help get online the 4 billion people who are without internet access.