Senior IP RTL Design Engineer

Microsoft

Jul 23, 2024

Applications are closed

Job
Full-time
Senior Level
Design
Software Engineering
$117.2K - $229.2K
Hillsboro

Requirements

Required Qualifications:
7+ years of related technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
Proficient in Verilog/System Verilog coding constructs.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
Master's degree in Electrical Engineering or BS in Computer/Electrical Engineering with 2+ years of experience.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs.
Experience with IPXACT.
Understanding of Computer Architecture fundamentals
Ability to write scripts using Python, Tcl, Perl etc.
Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Proficiency with UPF (Low power intent).
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Applied understanding of low power design principles.
Understanding in design closure challenges in power and clock domain crossings.
Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints.

Responsibilities

Own subsystem integrating several industry standard IPs.
Specifying and micro-architecting digital blocks, and performing concept studies to guide performance, power, and gate count.
Write RTL code for blocks based on architectural specifications.
Participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team.
Assess and then refine the implementation for area, power, and performance.
Define, create, and maintain project documentation, including design documents with analysis reports.
Collaborate with architecture, subsystem owners, and IP providers to configure the IP to maximize performance for various use cases.
Grow your micro-architectural knowledge of your own blocks as well as other blocks in the SoC.
Describe the power intent of the design through UPF.
Perform design quality checks such as Lint, CDC, RDC, Low Power Intent, Synthesis, Logic Equivalence.
Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
Automate tasks using scripting for efficiency.
Delight your customers who receive your deliverable by providing high quality functional block on schedule and with professional integrity.
Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.
Challenge the status quo with a growth mindset.

FAQs

What is the primary focus of the Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team?

The primary focus of the SCHIE team is to deliver the core infrastructure and foundational technologies for Microsoft's cloud services, powering over 200 online businesses globally, while ensuring high efficiency, smart growth, and a trusted experience for customers and partners.

What role will the Senior IP RTL Design Engineer play within the Cloud Computer Development Organization (CCDO)?

The Senior IP RTL Design Engineer will own subsystems integrating several industry-standard IPs, specify and micro-architect digital blocks, write RTL code, participate in design verification, and collaborate with cross-functional teams to optimize cloud infrastructure and ensure high-quality deliverables.

What are the required qualifications for this position?

The required qualifications include having 7+ years of related technical engineering experience, or a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with relevant experience, or a Master’s or Doctorate degree in the same fields. Additionally, knowledge of front-end tools and proficiency in Verilog/System Verilog coding constructs are required.

What specific skills are preferred for candidates applying for this position?

Preferred qualifications include a Master's degree in Electrical Engineering, experience with standard interface protocols like AXI and APB, familiarity with ARM Fabric IPs, proficiency in EDA tools, scripting abilities in languages such as Python or Tcl, and an understanding of design closure challenges in power and clock domain crossings.

What responsibilities will the Senior IP RTL Design Engineer have regarding design quality checks?

The Senior IP RTL Design Engineer will be responsible for performing design quality checks such as Lint, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), Low Power Intent checks, synthesis, and logic equivalence.

What kind of work culture and values does Microsoft promote for this role?

Microsoft promotes a culture of inclusion, respect, integrity, and accountability, encouraging employees to embody their values in their daily work, challenge the status quo, and maintain a growth mindset in collaboration with cross-functional teams.

What is the typical base pay range for the Senior IP RTL Design Engineer role in the U.S.?

The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year, with higher ranges applicable to specific locations like the San Francisco Bay area and New York City metropolitan area, where it is USD $153,600 - $250,200 per year.

Until when can candidates apply for the Senior IP RTL Design Engineer position?

Candidates can apply for the role until August 13, 2024.

What security requirements must candidates meet for this role?

Candidates must meet Microsoft, customer, or government security screening requirements, which include passing the Microsoft Cloud background check upon hire or transfer and every two years thereafter.

How does Microsoft ensure equal employment opportunities for applicants?

Microsoft is an equal opportunity employer and considers all qualified applicants for employment without regard to various protected characteristics, ensuring a fair and inclusive application process.

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