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DFT Engineer Intern

Logo of Intel Corporation

Intel Corporation


2mo ago

🚀 Summer Internship

Hillsboro +1

AI generated summary

  • Candidates must be pursuing a Masters or PhD in Electrical Engineering or related STEM field, with at least 6 months of experience in logic design, verification, Verilog or System Verilog, scripting languages like Perl or Python, and preferably experience in DFT (ATPG, Memory BIST, JTAG, etc.).
  • The DFT Engineer Intern at Intel will work on various aspects of Design for Test (DFT) including RTL design, validation automation, timing analysis, trace pattern generation, and post-Si debug in domains such as TAP Controller, Scan, MBIST, and IO DFT.

Summer Internship

Software Engineering, Design•Hillsboro, Phoenix


  • Are you passionate about computer graphics and disrupting the industry with your innovation, and working with leading Engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve Best-In-Class visual experiences that enable Users to immerse themselves in a new visual future? Then the GPU Hardware IP team has an opportunity for you. Our Hardware development team designs and validates the future of Intel Graphics. We are looking for a Graduate Intern to work with our DFT Design Engineering team.


  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork, classes and project work, internships, and/or work experience.
  • Minimum Qualifications:
  • You must be pursuing a Masters Degree or PhD Degree in Electrical Engineering or related STEM degree and 6+ months of experience in one or more of the following areas:
  • Logic design, validation/verification, or digital electronics
  • Verilog or System Verilog
  • Microprocessors, computer system or graphics architecture
  • Scripting languages such as Perl or Python
  • Preferred Qualifications:
  • Work or educational experience in DFT (ATPG, Memory BIST, JTAG, etc.)

Education requirements

Currently Studying

Area of Responsibilities

Software Engineering


  • As an integral member of the Graphics Hardware DFT group, you will be involved in, but not limited to, Design RTL, GLS, validation automation, and/or timing analysis in the following DFT domains: TAP Controller, Scan, Array DFT, PBIST, MBIST, IO DFT, PLL DFT or HVM Reset. You may also contribute with trace pattern generation efforts and post-Si debug


Work type

Full time

Work mode



Hillsboro, Phoenix