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Standard Cell Design Intern

Applications are closed

  • Internship
    Off-cycle Internship
  • Design
  • Hillsboro
    San Diego
    Santa Clara


  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
  • Minimum Qualifications:
  • Candidate must be currently pursuing a Master’s degree or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience/Knowledge in the following:
  • Basic understanding of standard cell circuit concepts, including logic gates, flip-flops, and complex combinational circuits.
  • VLSI design or Circuit design (Familiarity with timing measurements such as setup time, hold time, and propagation delay).
  • Experience with layout design and knowledge of layout techniques for CMOS processes.
  • Experience in using EDA tools for design (such as cadence virtuoso or custom compiler), simulation (such as Hspice or liberate or primesim or finesim) and verification.
  • Preferred Qualifications:
  • Experience/Knowledge in the following:
  • Previous internship or project experience in IC design or related field.
  • Coursework in VLSI design, semiconductor physics, or digital electronics.
  • Familiarity with scripting languages such as Python, Perl, or Tcl for design automation.


  • Assist in the design and optimization of standard cells for digital integrated circuits.
  • Perform basic timing analysis and characterization of standard cells.
  • Collaborate with the layout team to ensure design rules and quality standards are met.
  • Utilize CAD tools for schematic entry, simulation, and layout verification.
  • Participate in design reviews and provide feedback on circuit performance.
  • Support the team in debugging and resolving design issues.
  • Document design processes and results for future reference and improvement.

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