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ASIC Design Verification Engineer, Machine Learning, University Graduate

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Google

Mar 11, 2024

Applications are closed

  • Job
    Full-time
    Entry Level
  • Data
    Software Engineering
  • £105K - £152K
  • Sunnyvale

Requirements

  • Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
  • Academic, educational, internship, or project experience designing or verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs.
  • Experience coding in SystemVerilog or Verilog.
  • Preferred Qualifications:
  • Master's or Doctorate degree in Electrical Engineering or related field.
  • Experience with verification methodology such as UVM/OVM/VMM.
  • Experienced with the full verification life cycle.
  • Knowledge of SystemVerilog.
  • Strong problem solver, communicator, and team player.

Responsibilities

  • Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
  • Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Technology
Industry
10,001+
Employees
1998
Founded Year

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