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Job

ASIC RTL Design Engineer, ML Accelerators, University Graduate

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Google

•

3mo ago

đź’Ľ Graduate Job

Sunnyvale +1

🤑 $105K - $152K
⌛ Closed
Applications are closed

Graduate Job

Design•Sunnyvale, Madison

Description

  • Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
  • As a key member of the team, you manage projects in multiple areas with your expertise. You also monitor the performance of vendors working on projects and evaluate new technologies.

Requirements

  • Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
  • Experience with a scripting language (e.g., Perl or Python)
  • Preferred Qualifications:
  • Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent practical experience.
  • Coursework in Digital Design, Computer Architecture, Digital Circuit Design, VLSI Design, Design-for-Test and/or Design Verification.
  • Experience with IP development.
  • Familiarity with Design Tools related to Verilog simulation, synthesis, static timing analysis, formal verification, power analysis, and/or place and route.

Education requirements

Currently Studying
Bachelors
Masters
PhD

Area of Responsibilities

Design

Responsibilities

  • Contribute to the microarchitecture and RTL coding of blocks, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
  • Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
  • Develop novel ways to automate generation of complex RTL designs.
  • Contribute to design methodology, libraries, and code review.

Details

Work type

Full time

Work mode

office

Location

Sunnyvale, Madison

Salary

105000 - 152000 USD