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ASIC RTL Design Engineer, ML Accelerators, University Graduate

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Google

Mar 11

Applications are closed

  • Job
    Full-time
    Entry Level
  • Design
  • $105K - $152K
  • Sunnyvale, +1

Requirements

  • Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
  • Experience with a scripting language (e.g., Perl or Python)
  • Preferred Qualifications:
  • Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent practical experience.
  • Coursework in Digital Design, Computer Architecture, Digital Circuit Design, VLSI Design, Design-for-Test and/or Design Verification.
  • Experience with IP development.
  • Familiarity with Design Tools related to Verilog simulation, synthesis, static timing analysis, formal verification, power analysis, and/or place and route.

Responsibilities

  • Contribute to the microarchitecture and RTL coding of blocks, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
  • Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
  • Develop novel ways to automate generation of complex RTL designs.
  • Contribute to design methodology, libraries, and code review.

Technology
Industry
10,001+
Employees
1998
Founded Year

Mission & Purpose

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.