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Physical Design Engineer For CPU Core IP

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Intel Corporation


26d ago

đź’Ľ Graduate Job


AI generated summary

  • You need a degree in Computer or Electrical Engineering, experience in IC design tools, PV convergence, physical design verification, scripting, and successful experience with logic block synthesis. Ideally, you also have exposure to CPU microarchitecture and strong knowledge of physical design best practices.
  • You will be responsible for performing synthesis, place and route, power, timing checks, and design closure for high speed CPU core design. Help refine synthesis flow and recommend better design practices for reproducible design convergence.

Graduate Job

Software Engineering•Hillsboro


  • As a member of E-core CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap.


  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
  • Minimum Qualifications:
  • Bachelors in Computer Engineering or Electrical Engineering or related technical field with 1+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related technical field.
  • Experience in:
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
  • PV convergence (including static timing and power analysis).
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby).
  • Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP.
  • Preferred Qualifications:
  • Industry experience/exposure with CPU Micro-Architecture
  • Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques
  • Strong knowledge of RTL to GDS methodologies and formal equivalence
  • Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)
  • Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Education requirements


Area of Responsibilities

Software Engineering


  • Synthesis and Place and Route using industry standard tools for high speed CPU core design.
  • Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.
  • Develop strategies to deliver reproducible design convergence results.
  • Help to create and refine synthesis flow for the project team.
  • Develop and recommend better design method practices to enable better synthesis convergence.
  • The ideal candidate will exhibit behavioral traits that demonstrate:
  • Willingness to work with others in a highly complex decision space.
  • Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule.
  • Excellent verbal and written communication and collaboration skills.


Work type

Full time

Work mode