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Physical Design Engineer For CPU Core IP

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  • Job
    Full-time
    Junior Level
  • Software Engineering
  • Hillsboro

Requirements

  • You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
  • Minimum Qualifications:
  • Bachelors in Computer Engineering or Electrical Engineering or related technical field with 1+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related technical field.
  • Experience in:
  • Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure.
  • PV convergence (including static timing and power analysis).
  • Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby).
  • Demonstrated success in one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP.
  • Preferred Qualifications:
  • Industry experience/exposure with CPU Micro-Architecture
  • Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques
  • Strong knowledge of RTL to GDS methodologies and formal equivalence
  • Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus)
  • Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Responsibilities

  • Synthesis and Place and Route using industry standard tools for high speed CPU core design.
  • Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure.
  • Develop strategies to deliver reproducible design convergence results.
  • Help to create and refine synthesis flow for the project team.
  • Develop and recommend better design method practices to enable better synthesis convergence.
  • The ideal candidate will exhibit behavioral traits that demonstrate:
  • Willingness to work with others in a highly complex decision space.
  • Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule.
  • Excellent verbal and written communication and collaboration skills.

FAQs

What will be the primary focus of this role as a Physical Design Engineer for CPU Core IP?

The primary focus of this role will be designing the latest core IP for cutting edge compute processors across various segments such as client, server, IOTG, and AI, with a focus on power efficiency and innovation.

What kind of microprocessor architecture will you be working on?

You will be working on state-of-the-art microprocessor architecture on the most advanced and latest process technologies.

In which segments of Intel's compute roadmap are the core designs developed in this role present?

Core designs developed in this role are present in nearly all segments of Intel's compute roadmap.

Technology
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Employees
1968
Founded Year

Mission & Purpose

Intel’s mission is to shape the future of technology to help create a better future for the entire world. By pushing forward in fields like AI, analytics and cloud-to-edge technology, Intel’s work is at the heart of countless innovations. From major breakthroughs like self-driving cars and rebuilding the coral reefs, to things that make everyday life better like blockbuster effects and improved shopping experiences — they’re all powered by Intel technology. With a career at Intel, you have the opportunity to help make the future more wonderful for everyone.