FAQs
What is the primary focus of the Senior Mask Layout Design Engineer position?
The primary focus of the position is to perform physical layout for mixed-signal functions in state-of-the-art sub-micron CMOS technologies and work collaboratively with a multidisciplinary team.
What tools will I be using in this role?
You will be using Cadence tools, particularly Virtuoso, along with verification tools such as Dracula, Hercules, and Calibre.
What type of experience is required for this position?
At least 5+ years of hands-on layout design experience is required, along with a deep understanding of analog circuit layout concepts in submicron CMOS technologies.
Is a specific degree required to apply for this position?
A BS in Electrical Engineering or equivalent experience is required to apply for this position.
Will I be working alone or as part of a team?
You will be working as part of a collaborative and multi-functional team of engineers from diverse disciplines, including Photonics, CMOS, Electronics, and Systems.
What scripting languages should I be familiar with for this role?
Proficiency in scripting languages such as Perl, Python, and Skill is needed, along with knowledge of DRC and LVS checking flows.
What additional skills are important for this position?
Good interpersonal skills, a positive attitude, and the ability to work optimally in a team are important for success in this role.
What will my responsibilities include in this job?
Your responsibilities will include floor planning, custom layout, verifying designs against design rules and schematics, and interacting with foundries for fill and post-processing.
Is there opportunity for growth in this role?
Yes, this position is part of a growing group at NVIDIA, which offers opportunities for professional development and advancement within the company.
What kind of projects will I be involved in?
You will be involved in handling high-speed mixed-signal circuit designs and ASIC integration for VLSI products.